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Clock signal
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#	Item
151	Real-Time Station Clock Synchronization for GNSS Integrity Monitoring Johannes Mach, Ingrid Deuster, Robert Wolf, Theo Zink IfEN Gesellschaft für Satellitennavigation mbH (IfEN GmbH), D[removed]Poing, Germany BIOGRAPHY Add to Reading List Source URL: www.ifen.com Language: English - Date: 2010-06-30 09:18:44 Linear filters Filter theory Robot control Kalman filter Estimation theory Allan variance Filter Electronic filter Least squares Electronic engineering Statistics Signal processing
152	DYNAMIC FREQUENCY AND VOLTAGE SCALING FOR A MULTIPLE-CLOCK-DOMAIN MICROPROCESSOR MULTIPLE CLOCK DOMAINS IS ONE SOLUTION TO THE INCREASING PROBLEM OF PROPAGATING THE CLOCK SIGNAL ACROSS INCREASINGLY LARGER AND Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-01-21 17:37:54 Central processing unit Parallel computing Microprocessors Energy conservation Alpha 21264 Dynamic voltage scaling Frequency scaling Multi-core processor Out-of-order execution Computer hardware Computer architecture Computing
153	Clock and Timing ICs for Wireline Applications In Networks and Beyond Analog Devices, Inc. (ADI), is a global leader in high performance semiconductors for signal processing applications and a leader in integrated circui Add to Reading List Source URL: www.analog.com Language: English - Date: 2011-10-10 15:39:55 Oscillators Electronic design Electronic circuits Digital electronics Logic families Phase-locked loop Low-voltage differential signaling Clock signal Jitter Electronic engineering Electronics Electromagnetism
154	Microsoft Word - EndtoEndRetiming6.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-05-01 11:48:41 Electronic design automation Clock signal Retiming Operations research Electrical circuits Clock skew Physical design Clock distribution network Mathematical optimization Electronic engineering Formal methods Electronics
155	Adaptatone Millennium System Master TM Add to Reading List Source URL: edwards-signals.com Language: English - Date: 2004-06-04 12:26:39 Addressability RS-485 Ringtone Notification system Signal tone Electronics Technology Electronic engineering Signaling Clock
156	Crystal-less USB operation on Kinetis MCUs Add to Reading List Source URL: cache.freescale.com Language: English - Date: 2014-11-04 20:52:16 Freescale Semiconductor Oscillators Universal Serial Bus ARM architecture Clock signal Phase-locked loop Tegra TI MSP430 Atmel AVR Electronic engineering Computer hardware Electronics
157	VLSI DESIGN 2001, Vol. 12, No. 3, pp[removed]Reprints available directly from the publisher Photocopying permitted by license only (C[removed]OPA (Overseas Publishers Association) N.V. Add to Reading List Source URL: downloads.hindawi.com Language: English - Date: 2014-05-08 05:38:12 Electronics Electrical circuits Digital circuits Digital signal processing Adder Binary logic Clock signal Multiply–accumulate operation Propagation delay Electronic engineering Computer arithmetic Electrical engineering
158	1298 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 16, NO. 5, SEPTEMBER/OCTOBER[removed]Gb/s Burst-Mode Clock and Data Recovery Based on Semiblind Oversampling for PONs: Add to Reading List Source URL: www.photonics.ece.mcgill.ca Language: English - Date: 2011-02-01 22:05:11 Digital signal processing Synchronization Digital electronics Oscillators Clock signal Jitter Phase-locked loop Clock recovery SerDes Electronic engineering Electronics Electrical engineering
159	Invited Paper 20-GSample/s (10 GHz 2 Clocks) Burst-Mode CDR Based on Injection Locking and Space Sampling for Multiaccess Networks Volume 4, Number 5, October 2012 Add to Reading List Source URL: www.photonics.ece.mcgill.ca Language: English - Date: 2012-09-20 11:35:24 Oscillators Data transmission Network performance Jitter Synchronization Clock signal Clock recovery Phase-locked loop Phase noise Electronic engineering Electronics Telecommunications engineering
160	IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 20, NO. 5, MARCH 1, [removed]A Standalone Burst-Mode Receiver With Clock and Data Recovery, Clock Phase Alignment, and Add to Reading List Source URL: www.photonics.ece.mcgill.ca Language: English - Date: 2010-02-23 10:42:02 Data transmission Network performance Clock signal Electrical circuits Bit error rate Ratios Passive optical network Clock recovery Throughput Electronic engineering Telecommunications engineering Electronics

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